Argitalpenak (17) Ikertzaileren baten partaidetza izan duten argitalpenak

1999

  1. Clock distribution using multiple voltages

    Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, pp. 145-150

  2. Efficient crosstalk estimation

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 266-272

  3. El sector de fabricación de vehículos y sus piezas en las talas input-output de Navarra (1995)

    Jornadas de Estudio sobre la Economía Navarra basadas en las Tablas Input-Output: 22 y 23 de octubre de 1998 (Instituto de Estadística de Navarra), pp. 183-202

  4. El subsector de conservas de frutas y hortalizas en Navarra: Evolución y análisis a través de las tablas input-output

    Jornadas de Estudio sobre la Economía Navarra basadas en las Tablas Input-Output: 22 y 23 de octubre de 1998 (Instituto de Estadística de Navarra), pp. 249-264

  5. FAR-DS: Full-plane AWE Routing with Driver Sizing

    Proceedings - Design Automation Conference, pp. 84-89

  6. Integrated algorithm for combined placement and libraryless technology mapping

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

  7. La narrativa anglo-americana de la propiedad

    Cuadernos Empresa y Humanismo ( Serie de monografías ), Núm. 75, pp. 4-82

  8. Low NOx LPP combustion test facility with four transparent windows for non intrusive flow diagnostics

    Proceedings of the ASME Turbo Expo

  9. Marsh: min-area retiming with setup and hold constraints

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

  10. Non-Hanan routing

    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, Núm. 3, pp. 436-444

  11. Non-hanan routing

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Núm. 4, pp. 436-444

  12. On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits

    IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 245-248

  13. Optimizing large multiphase level-clocked circuits

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Núm. 9, pp. 1249-1264

  14. Retiming control logic

    Integration, the VLSI Journal, Vol. 28, Núm. 1, pp. 33-53

  15. Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model

    Proceedings of the International Symposium on Physical Design, pp. 133-138

  16. Timing-driven partitioning for two-phase domino and mixed static/domino implementations

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

  17. Trust and Filipino family business

    INTERNATIONAL BUSINESS ETHICS: CHALLENGES AND APPROACHES