Power-Delay optimizations in gate sizing

  1. Sapatnekar, S.S.
  2. Chuang, W.
Revue:
ACM Transactions on Design Automation of Electronic Systems

ISSN: 1084-4309

Année de publication: 2000

Volumen: 5

Número: 1

Pages: 98-114

Type: Article

DOI: 10.1145/329458.329473 GOOGLE SCHOLAR