Delay and area optimization for discrete gate sizes under double-sided timing constraints

  1. Chuang, Weitong
  2. Sapatnekar, Sachin S.
  3. Hajj, Ibrahim N.
Actes de conférence:
Proceedings of the Custom Integrated Circuits Conference

ISSN: 0886-5930

ISBN: 0780308263

Année de publication: 1993

Type: Communication dans un congrès