Sanhita
Sapatnekar
Personal Predoctoral
Publicaciones (544) Publicaciones de Sanhita Sapatnekar
2024
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2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
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3SAT on an all-to-all-connected CMOS Ising solver chip
Scientific Reports, Vol. 14, Núm. 1
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An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
ACM Transactions on Design Automation of Electronic Systems, Vol. 29, Núm. 4
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Automated synthesis of mixed-signal ML inference hardware under accuracy constraints
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
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Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
Proceedings - International Symposium on High-Performance Computer Architecture
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MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On Error Correction for Nonvolatile Processing-In-Memory
Proceedings - International Symposium on Computer Architecture
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On Gate Flip Errors in Computing-In-Memory
Proceedings -Design, Automation and Test in Europe, DATE
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OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education
Proceedings of the IEEE VLSI Test Symposium
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Reinforcing the Connection between Analog Design and EDA (Invited Paper)
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2023
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A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts
ACM Transactions on Design Automation of Electronic Systems, Vol. 28, Núm. 5
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A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
ACM Transactions on Design Automation of Electronic Systems, Vol. 29, Núm. 1
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A Multicore GNN Training Accelerator
Proceedings of the International Symposium on Low Power Electronics and Design
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A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 9, Núm. 1, pp. 29-37
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A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, Núm. 12, pp. 4844-4857
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An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture
Nature Electronics, Vol. 6, Núm. 10, pp. 771-778
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An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer
Microelectronics Reliability, Vol. 142
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Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design
Proceedings - International Symposium on Quality Electronic Design, ISQED
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AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells
Proceedings -Design, Automation and Test in Europe, DATE