(FCEE) Empresa
Departamento académico
Intel Corporation, Systems Research Center, Systems Technology Lab.
San Jose, EE. UU.Publicaciones en colaboración con investigadores/as de Intel Corporation, Systems Research Center, Systems Technology Lab. (26)
2024
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Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2023
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A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts
ACM Transactions on Design Automation of Electronic Systems, Vol. 28, Núm. 5
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GNN-Based Hierarchical Annotation for Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, Núm. 9, pp. 2801-2814
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Machine Learning for Analog Layout
Machine Learning Applications in Electronic Design Automation (Springer Singapore), pp. 505-544
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Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2022
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A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement
Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
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Analog/Mixed-Signal Layout Optimization using Optimal Well Taps
Proceedings of the International Symposium on Physical Design
2021
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ALIGN: A System for Automating Analog Layout
IEEE Design and Test, Vol. 38, Núm. 2, pp. 8-18
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Common-Centroid Layouts for Analog Circuits: Advantages and Limitations
Proceedings -Design, Automation and Test in Europe, DATE
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Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
2020
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GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
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GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020)
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Learning from experience: Applying ML to analog circuit design
Proceedings of the International Symposium on Physical Design
2019
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INVITED: ALIGN - Open-source analog layout automation from the ground up
Proceedings - Design Automation Conference
2015
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RTL Synthesis: From Logic Synthesis to Automatic Pipelining
Proceedings of the IEEE, Vol. 103, Núm. 11, pp. 2061-2075
2008
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A framework for block-based timing sensitivity analysis
Proceedings - Design Automation Conference
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A framework for block-based timing sensitivity analysis
2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2
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A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Núm. 1, pp. 160-173
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Reinventing EDA with manycore processors
2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2
2007
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A general model for performance optimization of sequential systems
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD