(FCEE) Empresa

2004

1. A chip-level electrostatic discharge simulation strategy

   IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

2. A method for correcting the functionality of a wire-pipelined circuit

   Proceedings - Design Automation Conference

3. A predictive distributed congestion metric and its application to technology mapping

   Proceedings of the International Symposium on Physical Design

4. Accurate estimation of global buffer delay within a floorplan

   IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

5. Early-stage power grid analysis for uncertain working modes

   Proceedings of the International Symposium on Physical Design

6. Fast comparisons of circuit implementations

   Proceedings - Design, Automation and Test in Europe Conference and Exhibition

7. Hierarchical random-walk algorithms for power grid analysis

   Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

8. High-performance power grids for nanometer technologies

   Proceedings of the IEEE International Conference on VLSI Design

9. High-performance power grids for nanometer technologies

   17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

10. Logical effort based technology mapping

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

11. On the selection of on-chip inductors for the optimal VCO design

    Proceedings of the Custom Integrated Circuits Conference

12. On the selection of on-chip inductors for the optimal VCO design

    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE

13. Optimization of integrated spiral inductors using sequential quadratic programming

    Proceedings -Design, Automation and Test in Europe, DATE

14. Optimization of integrated spiral inductors using sequential quadratic programming

    Proceedings - Design, Automation and Test in Europe Conference and Exhibition

15. Reaching inflation stability

    Journal of Money, Credit and Banking

16. Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

17. Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

    IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS

18. Topology optimization of structured power/ground networks

    Proceedings of the International Symposium on Physical Design

19. Tradeoffs between gate oxide leakage and delay for dual <i>T_ox</i> circuits

    41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004

20. Tradeoffs between gate oxide leakage and delay for dual T ox circuits

    Proceedings - Design Automation Conference