Publicaciones (11) Publicaciones en las que ha participado algún/a investigador/a

1996

  1. A practical algorithm for retiming level-clocked circuits

    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS

  2. Clock tree synthesis for multi-chip modules

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

  3. Clock tree synthesis for multi-chip modules

    1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS

  4. Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

    Proceedings - IEEE International Symposium on Circuits and Systems

  5. Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4

  6. El papel del Estado en las pensiones de jubilación en Navarra

    Actas del Primer Congreso de Economía de Navarra

  7. Optimal design of macrocells for low power and high speed

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 9, pp. 1160-1166

  8. Practical algorithm for retiming level-clocked circuits

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

  9. Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 10, pp. 1237-1248

  10. Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 8, pp. 1001-1011

  11. Wiresizing with buffer placement and sizing for power-delay tradeoffs

    Proceedings of the IEEE International Conference on VLSI Design