(FCEE) Empresa

2001

1. A new structural pattern matching algorithm for technology mapping

   Proceedings - Design Automation Conference, pp. 371-376

2. A new structural pattern matching algorithm for technology mapping

   38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001

3. A practical methodology for early buffer and wire resource allocation

   Proceedings - Design Automation Conference, pp. 189-194

4. A practical methodology for early buffer and wire resource allocation

   38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001

5. A survey on multi-net global routing for integrated circuits

   Integration, the VLSI Journal, Vol. 31, Núm. 1, pp. 1-49

6. Buffered Steiner trees for difficult instances

   Proceedings of the International Symposium on Physical Design

7. Circuit-aware on-chip inductance extraction

   Proceedings of the Custom Integrated Circuits Conference

8. Circuit-aware on-chip inductance extraction

   PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE

9. Design closure with cell-based synthesis

   IEEE Design and Test of Computers, Vol. 18, Núm. 5, pp. 112-119

10. El capital moral de la empresa y la creación de valor para el accionista: la importancia del carácter del directivo

    Aedipe: Revista de la Asociación Española de Dirección de Personal, Núm. 19, pp. 9-18

11. Exact and efficient crosstalk estimation

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Núm. 7, pp. 858-866

12. Hybrid structured clock network construction

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 333-336

13. Performance driven global routing through gradual refinement

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 481-483

14. Proceedings of the International Symposium on Physical Design: Foreword

    Proceedings of the International Symposium on Physical Design

15. Recuerdos de un seminario con Joseph E. Stiglitz, Premio Nobel de Economía 2001

    Nuevas tendencias, Núm. 45, pp. 64-66

16. Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

17. Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

    ICCAD 2001: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS

18. Saber, vender, saber: la propiedad intelectual y el comercio en la era digital

    Ediciones Deusto

19. Steiner tree optimization for buffers, blockages, and bays

    Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 399-402

20. Steiner tree optimization for buffers, blockages, and bays

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Núm. 4, pp. 556-562