Publicaciones en colaboración con investigadores/as de University of Minnesota (395)

2024

  1. 2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference

  2. 3SAT on an all-to-all-connected CMOS Ising solver chip

    Scientific Reports, Vol. 14, Núm. 1

  3. Automated synthesis of mixed-signal ML inference hardware under accuracy constraints

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

  4. Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

  5. ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI

    Proceedings - International Symposium on High-Performance Computer Architecture

  6. OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education

    Proceedings of the IEEE VLSI Test Symposium

  7. Reinforcing the Connection between Analog Design and EDA (Invited Paper)

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

2023

  1. A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts

    ACM Transactions on Design Automation of Electronic Systems, Vol. 28, Núm. 5

  2. A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

    ACM Transactions on Design Automation of Electronic Systems, Vol. 29, Núm. 1

  3. A Multicore GNN Training Accelerator

    Proceedings of the International Symposium on Low Power Electronics and Design

  4. A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)

    IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 9, Núm. 1, pp. 29-37

  5. A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, Núm. 12, pp. 4844-4857

  6. An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture

    Nature Electronics, Vol. 6, Núm. 10, pp. 771-778

  7. An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

    Microelectronics Reliability, Vol. 142

  8. Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design

    Proceedings - International Symposium on Quality Electronic Design, ISQED

  9. AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells

    Proceedings -Design, Automation and Test in Europe, DATE

  10. Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, Núm. 9, pp. 2782-2795

  11. Deep Learning for Analyzing Power Delivery Networks and Thermal Networks

    Machine Learning Applications in Electronic Design Automation (Springer Singapore), pp. 115-150

  12. Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications

    Proceedings -Design, Automation and Test in Europe, DATE

  13. Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN

    Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium