Publicaciones (16) Publicaciones en las que ha participado algún/a investigador/a

1996

  1. A practical algorithm for retiming level-clocked circuits

    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS

  2. Clock tree synthesis for multi-chip modules

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

  3. Clock tree synthesis for multi-chip modules

    1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS

  4. Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

    Proceedings - IEEE International Symposium on Circuits and Systems

  5. Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4

  6. El papel del Estado en las pensiones de jubilación en Navarra

    Actas del Primer Congreso de Economía de Navarra

  7. Estetica e metafisica in Fray Luis de León

    RIVISTA DI ASCETICA E MISTICA, Vol. XXI, Núm. 1, pp. 29-50

  8. Estética y nueva retórica en Juan de Mairena

    El Basilisco: Revista de materialismo filosófico, Núm. 21, pp. 66-67

  9. La obra de arte como diálogo lúdico

    Diálogo y retórica

  10. La teoría del arte en Plotino

    Helmantica: Revista de filología clásica y hebrea, Tomo 47, Núm. 142, pp. 27-57

  11. Optimal design of macrocells for low power and high speed

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 9, pp. 1160-1166

  12. Practical algorithm for retiming level-clocked circuits

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

  13. Regulación por resultados en el sector sanitario: el uso de los años de vida ajustados por la calidad

    Hacienda Pública Española / Review of Public Economics, Núm. 139, pp. 37-46

  14. Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 10, pp. 1237-1248

  15. Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, Núm. 8, pp. 1001-1011

  16. Wiresizing with buffer placement and sizing for power-delay tradeoffs

    Proceedings of the IEEE International Conference on VLSI Design