A methodology and framework to assist in the architecture design and functional verification of complex electronic systems
- Tomasena, Koldo
- Igone Velez Isasmendi Zuzendaria
- Juan Sevillano Berasategui Zuzendaria
Defentsa unibertsitatea: Universidad de Navarra
Fecha de defensa: 2013(e)ko uztaila-(a)k 12
- Andrés García-Alonso Montoya Presidentea
- Andoni Irizar Picón Idazkaria
- Jon Legarda Macon Kidea
- Miguel Soto Rodríguez Kidea
- Francisco Javier del Pino Suárez Kidea
Mota: Tesia
Laburpena
An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions