A general approach for identifying hierarchical symmetry constraints for analog circuit layout

  1. Kunal, K.
  2. Poojary, J.
  3. Dhar, T.
  4. Madhusudan, M.
  5. Harjani, R.
  6. Sapatnekar, S.S.
Actes de conférence:
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

ISSN: 1092-3152

Année de publication: 2020

Volumen: 2020-November

Type: Communication dans un congrès

DOI: 10.1145/3400302.3415685 GOOGLE SCHOLAR lock_openAccès ouvert editor
La source de données: Scopus