An efficient algorithm for low power pass transistor logic synthesis

  1. Shelar, R.S.
  2. Sapatnekar, S.S.
Konferenzberichte:
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

ISBN: 9780769514413

Datum der Publikation: 2002

Seiten: 87-92

Art: Konferenz-Beitrag

DOI: 10.1109/ASPDAC.2002.994890 GOOGLE SCHOLAR
Datenquelle: Scopus