An efficient algorithm for low power pass transistor logic synthesis
- Shelar, R.S.
- Sapatnekar, S.S.
Actes de conférence:
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
ISBN: 9780769514413
Année de publication: 2002
Pages: 87-92
Type: Communication dans un congrès