SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

  1. Sathyamurthy, H.
  2. Sapatnekar, S.S.
  3. Fishburn, J.P.
Revista:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ISSN: 0278-0070

Any de publicació: 1998

Volum: 17

Número: 2

Pàgines: 173-182

Tipus: Article

DOI: 10.1109/43.681267 GOOGLE SCHOLAR
Font de les dades: Scopus