Design of reconfigurable rf circuits for self-compensation

  1. GÓMEZ SALINAS, DÍDAC
Dirigida por:
  1. Diego César Mateo Peña Director/a

Universidad de defensa: Universitat Politècnica de Catalunya (UPC)

Fecha de defensa: 25 de enero de 2013

Tribunal:
  1. Roque José Berenguer Pérez Presidente
  2. Xavier Aragonès Cervera Secretario/a
  3. H. G. Stratigopoulos Vocal

Tipo: Tesis

Teseo: 114907 DIALNET

Resumen

In the last decade the constant scaling of CMOS technologies has allowed the implementation of complex integrated systems on chip (SOCs) where together with the digital part analogue processing and conditioning functionality is included. Each new technology node has allowed an increase of the integration density, an increase in functionality and a decrease of power consumption of the system. However, in each new technology node the uncertanity of the manufacturing process has increased due to the constant reduction of the minimum manufacturable dimension. Certain techniques are applied in the field of digital design in order to cope with the increasing amount of variability, unfortunately the research of equivalent techniques for analgoue circuits has been more limited due to their specific characteristics (sensitivity to parasitics, sensitivity to loading effects...). This thesis deals with the research of techniques that can increase the robustness to process variations of analogue integrated circuits. The first step was the delimitation of the field of study to the blocks a RF front-end (LNA,Mixer) suitable for wireless sensor networks. This election is justified by the fact that RF circuits are a sub-type of analogue design that is very sensitive to parasitics and loading effects (thus limiting the effectiveness of conventional techniques like negative feedback) and also circuits for wirless sensor networks have a limited power budget (thus limiting the amount of overdesing that can be applied). The second step has been the design of reference circuits in order to perform an evaluation of the impact of process variations on them, additionally it has been evaluated the impact of supply and temperature variations. Two strategies for LNA process variations compensation: the first one exploits intrinsic characteristics of the MOS transistor (carrier velocity saturation) while the second one is based on indirect test of electrical characteristics (dummy transistor monitoring). The approach taken for Mixer compensation is based on topological changes with the addition of auxiliary circuits if needed. Finally, with the results obtained for LNAs and Mixers two RF front-ends (uncompensated and compensated) have been designed. The comparison of PVT robustness between the two front-ends shows how is it possible to design circuits with equivalent electrical characteristics without overdesign.The last part of the thesis deals with the variability problem from the test point of view. It has been proposed the use of indirect test based on thermal measurements. Altough previous research on thermal testing exists a novel approach based on static temperature testing is proposed. Moreover, a temperature sensor designed under the paradigm of robustness to process variations is presented. Finally, the problem of thermal interferences is studied and a solution based on the use of spatial diversity for interference cancellation is proposed. In order to support the theoretical and simulation work presented in the thesis a test chip implemented in CMOS 65nm has been designed and some of the concepts presented have been experimentally verified.