A UNIFIED ALGORITHM FOR GATE SIZING AND CLOCK SKEW OPTIMIZATION TO MINIMIZE SEQUENTIAL-CIRCUIT AREA

  1. CHUANG, WT
  2. SAPATNEKAR, SS
  3. HAJJ, IN
Buch:
1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS

ISBN: 0-8186-4490-7

Datum der Publikation: 1993

Seiten: 220-223

Kongress: 1993 IEEE/ACM International Conference on Computer-Aided Design

Art: Konferenz-Beitrag

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Fuente de los datos: WoS