A UNIFIED ALGORITHM FOR GATE SIZING AND CLOCK SKEW OPTIMIZATION TO MINIMIZE SEQUENTIAL-CIRCUIT AREA

  1. CHUANG, WT
  2. SAPATNEKAR, SS
  3. HAJJ, IN
Liburua:
1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS

ISBN: 0-8186-4490-7

Argitalpen urtea: 1993

Orrialdeak: 220-223

Biltzarra: 1993 IEEE/ACM International Conference on Computer-Aided Design

Mota: Biltzar ekarpena

GOOGLE SCHOLAR
Datuen iturria: WoS