Sanhita
Sapatnekar
Personal Predoctoral
Universitat Politècnica de Catalunya
Barcelona, EspañaPublicacions en col·laboració amb investigadors/es de Universitat Politècnica de Catalunya (11)
2017
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Static timing analysis
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology (CRC Press), pp. 133-154
2016
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A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 6, pp. 2345-2358
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Ring oscillator clocks and margins
Proceedings - International Symposium on Asynchronous Circuits and Systems
2015
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A Retargetable and Accurate Methodology for Logic-IP-internal Electromigration Assessment
2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
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A retargetable and accurate methodology for logic-IP-internal electromigration assessment
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
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RTL Synthesis: From Logic Synthesis to Automatic Pipelining
Proceedings of the IEEE, Vol. 103, Núm. 11, pp. 2061-2075
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Reactive Clocks with Variability-Tracking Jitter
2015 33RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
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Reactive clocks with variability-Tracking jitter
Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015
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Stochastic and Topologically Aware Electromigration Analysis for Clock Skew
2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
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Stochastic and topologically aware electromigration analysis for clock skew
IEEE International Reliability Physics Symposium Proceedings
2007
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A general model for performance optimization of sequential systems
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD