Publicaciones en las que colabora con David del Río Orduña (15)

2024

  1. Area-Efficient SiGe BiCMOS LNA With Wideband Frequency Tuning Capability Across D and G Bands

    IEEE Transactions on Circuits and Systems I: Regular Papers

2022

  1. A 22-m Operation Range Semi-Passive UHF RFID Sensor Tag With Flexible Thermoelectric Energy Harvester

    IEEE Sensors Journal, Vol. 22, Núm. 20, pp. 19797-19808

2021

  1. Design and Layout Considerations of a D-Band SiGe LNA for Radiometric Applications

    36th Conference on Design of Circuits and Integrated Systems, DCIS 2021

2020

  1. A 21 m operation range RFID tag for “pick to light” applications with a photovoltaic harvester

    Micromachines, Vol. 11, Núm. 11, pp. 1-18

2019

  1. A Compact, Wideband, and Temperature Robust 67-90-GHz SiGe Power Amplifier with 30% PAE

    IEEE Microwave and Wireless Components Letters, Vol. 29, Núm. 5, pp. 351-353

  2. A High Accuracy 3.1V Voltage Limiter for Enabling High Performance RFID Sensor Applications

    Midwest Symposium on Circuits and Systems

  3. Review of Bandgap Voltage Reference Architectures for Long-Range Passive RFID Applications

    2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019

2018

  1. A CMOS Low Frequency Analog RFID Front-End for the IoT

    Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

  2. Project Based Learning Methodology Applied to Radiofrequency Subject

    Tecnología, Aprendizaje y Enseñanza de la Electrónica: TAEE 2018 : Actas del XIII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica, Tenerife, 20-22 de junio, 2018

  3. Variable-length transmission lines for self-healing systems and reconfigurable millimeter-wave integrated circuits

    2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings

2017

  1. Variable-Length Transmission Lines for Self-Healing Systems and Reconfigurable Millimeter-Wave Integrated Circuits

    2017 32ND CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)

2016

  1. Layout-aware design methodology for a 75 GHz power amplifier in a 55 nm SiGe technology

    Integration, the VLSI Journal, Vol. 52, pp. 208-216

2014

  1. Challenge Oriented Methodology for Analog Integrated Circuit Layout Design Training

    Libro de actas del XI Congreso de tecnologías, aprendizaje y enseñanza de la electrónica, TAEE 2014: 11,12 y 13 de Junio de 2014. Universidad de Deusto. Bilbao

  2. Challenge Oriented Methodology for Analog Integrated Circuit Layout Design Training

    PROCEEDINGS OF 2014 XI TECHNOLOGIES APPLIED TO ELECTRONICS TEACHING (TAEE)

  3. Challenge oriented methodology for analog integrated circuit layout design training

    Proceedings of XI Tecnologias Aplicadas a la Ensenanza de la Electronica (Technologies Applied to Electronics Teaching), TAEE 2014