(FCEE) Empresa
Departamento académico
Iowa State University
Ames, Estados UnidosPublicaciones en colaboración con investigadores/as de Iowa State University (40)
2001
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Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Núm. 5, pp. 577-589
1999
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Non-hanan routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Núm. 4, pp. 436-444
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Optimizing large multiphase level-clocked circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Núm. 9, pp. 1249-1264
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Retiming control logic
Integration, the VLSI Journal, Vol. 28, Núm. 1, pp. 33-53
1998
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A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS
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An algorithm for simulating power/ground networks using padé approximants and its symbolic implementation
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, Núm. 10, pp. 1372-1382
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Combined transistor sizing with buffer insertion for timing optimization
Proceedings of the Custom Integrated Circuits Conference
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Combined transistor sizing with buffer insertion for timing optimization
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS
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Efficient minarea retiming of large level-clocked circuits
Proceedings -Design, Automation and Test in Europe, DATE
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Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, Núm. 1, pp. 74-83
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Fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
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Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, Núm. 4, pp. 625-633
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Moment-based techniques for RLC clock tree construction
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 45, Núm. 1, pp. 69-79
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Routing tree topology construction to meet interconnect timing constraints
Proceedings of the International Symposium on Physical Design
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SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, Núm. 2, pp. 173-182
1997
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Improved algorithm for minimum-area retiming
Proceedings - Design Automation Conference
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Minimum area retiming with equivalent initial states
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
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Power estimation considering statistical IC parametric variations
Proceedings - IEEE International Symposium on Circuits and Systems
1996
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Clock tree synthesis for multi-chip modules
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
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Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits
Proceedings - IEEE International Symposium on Circuits and Systems