(FCEE) Empresa

1998

1. A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

   INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS

2. An algorithm for simulating power/ground networks using padé approximants and its symbolic implementation

   IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, Núm. 10, pp. 1372-1382

3. Aplicación del modelo de transporte con limitación de vehículos de distribución, al caso de optimización de la flota de camiones de una empresa conservera

   X Reunión ASEPELT-España: Albacete, 20-21 junio 1996. Resumen de comunicaciones

4. Combined transistor sizing with buffer insertion for timing optimization

   Proceedings of the Custom Integrated Circuits Conference

5. Combined transistor sizing with buffer insertion for timing optimization

   IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS

6. Efectividad de la cobertura en el mercado de futuros español

   Las finanzas del fin de siglo

7. Efficient minarea retiming of large level-clocked circuits

   Proceedings -Design, Automation and Test in Europe, DATE

8. Efficient retiming of large circuits

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, Núm. 1, pp. 74-83

9. Fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

   Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

10. Interleaving buffer insertion and transistor sizing into a single optimization

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, Núm. 4, pp. 625-633

11. Moment-based techniques for RLC clock tree construction

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 45, Núm. 1, pp. 69-79

12. Por qué cambiar el sistema de pensiones

    Ediciones Internacionales Universitarias (EIUNSA)

13. Routing tree topology construction to meet interconnect timing constraints

    Proceedings of the International Symposium on Physical Design

14. SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, Núm. 2, pp. 173-182

15. Technology mapping for domino logic

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

16. Technology mapping for domino logic

    1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN

17. Timing optimization of mixed static and domino logic

    Proceedings - IEEE International Symposium on Circuits and Systems

18. Timing optimization of mixed static and domino logic

    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6