(FCEE) Empresa

2005

1. A Small-Sample Study of the New-Keynesian Macro Model

   Working Papers ( Universidad de Navarra. Facultad de Ciencias Económicas y Empresariales )

2. A fast algorithm for power grid design

   Proceedings of the International Symposium on Physical Design

3. A high efficiency full-chip thermal simulation algorithm

   IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

4. A hybrid linear equation solver and its application in quadratic placement

   IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

5. A new approach to the use of satisfiability in false path detection

   Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

6. A predictive distributed congestion metric with application to technology mapping

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, Núm. 5, pp. 696-709

7. An efficient technology mapping algorithm targeting routing congestion under delay constraints

   Proceedings of the International Symposium on Physical Design

8. Appointments for 2005-2006 term

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems

9. BDD decomposition for delay oriented pass transistor logic synthesis

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Núm. 8, pp. 957-970

10. Buffering global interconnects in structured ASIC design

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

11. Buffering global interconnects in structured ASIC design

    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2

12. Congestion-aware topology optimization of structured power/ground networks

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, Núm. 5, pp. 683-695

13. Cómo sacar verdadero partido a los modelos de gestión: las certificaciones y evaluaciones analizadas desde la perspectiva de la generación de valor

    Qualitas hodie: Excelencia, desarrollo sostenible e innovación, Núm. 102, pp. 26-29

14. Designing optimized pipelined global interconnects: Algorithms and methodology impact

    Proceedings - IEEE International Symposium on Circuits and Systems

15. Early-stage power grid analysis for uncertain working modes

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, Núm. 5, pp. 676-682

16. El valor de las recomendaciones de consenso de los analistas financieros en el mercado de capitales español

    Working papers = Documentos de trabajo: Serie EC - (Instituto Valenciano de Investigaciones Económicas)

17. El valor de mercado del nivel de las recomendaciones de consenso en el mercado de capitales español

    Armonización y gobierno de la diversidad [Recurso electrónico]: XIII Congreso AECA. Comunicaciones presentadas. Oviedo, 22 a 24 de septiembre de 2005

18. Exact lower bound for the number of switches in series to implement a combinational logic cell

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

19. Fast comparisons of circuit implementations

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Núm. 12, pp. 1329-1339

20. Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC