Publicaciones en las que colabora con Jordi Cortadella Fortuny (8)

2017

  1. Static timing analysis

    Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology (CRC Press), pp. 133-154

2016

  1. A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 6, pp. 2345-2358

  2. Ring oscillator clocks and margins

    Proceedings - International Symposium on Asynchronous Circuits and Systems

2015

  1. A retargetable and accurate methodology for logic-IP-internal electromigration assessment

    20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

  2. RTL Synthesis: From Logic Synthesis to Automatic Pipelining

    Proceedings of the IEEE, Vol. 103, Núm. 11, pp. 2061-2075

  3. Reactive clocks with variability-Tracking jitter

    Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015

  4. Stochastic and topologically aware electromigration analysis for clock skew

    IEEE International Reliability Physics Symposium Proceedings

2007

  1. A general model for performance optimization of sequential systems

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD