Publicaciones en colaboración con investigadores/as de IEEE Computer Society (23)

2008

  1. A geometric programming-based worst case gate sizing method incorporating spatial correlation

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Núm. 2, pp. 295-308

  2. A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Núm. 1, pp. 160-173

  3. Body bias voltage computations for process and temperature compensation

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, Núm. 3, pp. 249-262

  4. Technology mapping using logical effort for solving the load-distribution problem

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Núm. 1, pp. 45-58

2007

  1. High-efficiency green function-based thermal simulation algorithms

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Núm. 9, pp. 1661-1675

  2. Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Núm. 6, pp. 624-636

2006

  1. Partition-based algorithm for power grid design using locality

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

  2. Placement of thermal vias in 3-D ICs using various thermal objectives

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

  3. Technology mapping algorithm targeting routing congestion under delay constraints

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

  4. Temperature-aware placement for SOCs

    Proceedings of the IEEE, Vol. 94, Núm. 8, pp. 1502-1517

2005

  1. Appointments for 2005-2006 term

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

  2. BDD decomposition for delay oriented pass transistor logic synthesis

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Núm. 8, pp. 957-970

  3. Fast comparisons of circuit implementations

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Núm. 12, pp. 1329-1339

  4. Gate oxide leakage and delay tradeoffs for dual-Tox circuits

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Núm. 12, pp. 1362-1375

  5. Statistical timing analysis under spatial correlations

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, Núm. 9, pp. 1467-1482

2002

  1. Buffered Steiner trees for difficult instances

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, Núm. 1, pp. 3-14

  2. Fast and exact transistor sizing based on iterative relaxation

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, Núm. 5, pp. 568-581

2001

  1. Exact and efficient crosstalk estimation

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Núm. 7, pp. 858-866

  2. Technology mapping for high-performance static CMOS and pass transistor logic designs

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, Núm. 5, pp. 577-589

2000

  1. Timing-driven partitioning and timing optimization of mixed static-domino implementations

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Núm. 11, pp. 1322-1336