Combined transistor sizing with buffer insertion for timing optimization

  1. Jiang, Yanbin
  2. Sapatnekar, Sachin S.
  3. Bamji, Cyrus
  4. Kim, Juho
Actes de conférence:
Proceedings of the Custom Integrated Circuits Conference

ISSN: 0886-5930

Année de publication: 1998

Pages: 605-608

Type: Communication dans un congrès