Combined transistor sizing with buffer insertion for timing optimization
- Jiang, Yanbin
- Sapatnekar, Sachin S.
- Bamji, Cyrus
- Kim, Juho
Actas:
Proceedings of the Custom Integrated Circuits Conference
ISSN: 0886-5930
Ano de publicación: 1998
Páxinas: 605-608
Tipo: Achega congreso