Layout-aware design methodology for a 75 GHz power amplifier in a 55 nm SiGe technology

  1. Del Rio, D.
  2. Gurutzeaga, I.
  3. Solar, H.
  4. Beriain, A.
  5. Berenguer, R.
Revue:
Integration, the VLSI Journal

ISSN: 0167-9260

Année de publication: 2016

Volumen: 52

Pages: 208-216

Type: Article

DOI: 10.1016/J.VLSI.2015.07.010 GOOGLE SCHOLAR
La source de données: Scopus