An efficient algorithm for low power pass transistor logic synthesis

  1. Shelar, RS
  2. Sapatnekar, SS
Libro:
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

ISBN: 0-7695-1441-3

Año de publicación: 2002

Páginas: 87-92

Congreso: 7th Asia and South Pacific Design Automation Conference/15th International Conference on VLSI Design

Tipo: Aportación congreso

GOOGLE SCHOLAR
Fuente de los datos: WoS