Combined transistor sizing with buffer insertion for timing optimization

  1. Jiang, YB
  2. Sapatnekar, SS
  3. Bamji, C
  4. Kim, JH
Buch:
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS

ISBN: 0-7803-4292-5

Datum der Publikation: 1998

Seiten: 605-608

Kongress: IEEE Custom Integrated Circuits Conference

Art: Konferenz-Beitrag

DOI: 10.1109/CICC.1998.695051 GOOGLE SCHOLAR
Fuente de los datos: WoS