Combined transistor sizing with buffer insertion for timing optimization

  1. Jiang, YB
  2. Sapatnekar, SS
  3. Bamji, C
  4. Kim, JH
Livre:
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS

ISBN: 0-7803-4292-5

Année de publication: 1998

Pages: 605-608

Congreso: IEEE Custom Integrated Circuits Conference

Type: Communication dans un congrès

DOI: 10.1109/CICC.1998.695051 GOOGLE SCHOLAR
La source de données: WoS