Combined transistor sizing with buffer insertion for timing optimization
- Jiang, YB
- Sapatnekar, SS
- Bamji, C
- Kim, JH
ISBN: 0-7803-4292-5
Argitalpen urtea: 1998
Orrialdeak: 605-608
Biltzarra: IEEE Custom Integrated Circuits Conference
Mota: Biltzar ekarpena