A geometric programming-based worst case gate sizing method incorporating spatial correlation

  1. Singh, J.
  2. Luo, Z.-Q.
  3. Sapatnekar, S.S.
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ISSN: 0278-0070

Year of publication: 2008

Volume: 27

Issue: 2

Pages: 295-308

Type: Article

DOI: 10.1109/TCAD.2007.913391 GOOGLE SCHOLAR
Data source: Scopus