A geometric programming-based worst case gate sizing method incorporating spatial correlation
- Singh, J.
- Luo, Z.-Q.
- Sapatnekar, S.S.
ISSN: 0278-0070
Argitalpen urtea: 2008
Alea: 27
Zenbakia: 2
Orrialdeak: 295-308
Mota: Artikulua
Aldizkaria:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems